Videos und Webinare

Targeting MATLAB Algorithms to FPGAs

Learn how you can target algorithms written in MATLAB to Altera FPGAs using HDL Coder. In this webinar, see how this workflow supports each phase of the FPGA design process including:

  • Converting floating-point MATLAB algorithms to fixed-point
  • Generating VHDL and Verilog code directly from MATLAB using HDL Coder
  • Optimizing the FPGA implementation for performance or resource utilization
  • Integrating the HDL code into designs using Quartus II and Qsys
  • Verifying the FPGA implementation in hardware with FPGA-in-the-loop

We also show how design teams can use a language-based FPGA design flow as well as how to integrate this workflow into Model-Based Design.

About the Presenters: 

Robert Anderson
is a Principal Application Engineer for signal processing and communications at MathWorks, with a focus on FPGA implementation.  Robert has over 25 years of experience in hardware design and implementation. He earned his MS. in electrical and computer engineering from Northwestern University.

Udayan Sinha is a Product Marketing Engineer focusing on digital signal processing solutions at Altera. He holds a BSEE from the University of California, Davis.

Die Arbeitsweise der folgenden Werkzeuge wird gezeigt

  • HDL Coder
  • HDL Verifier

Aufgezeichnet: 30 Apr 2013