HDL Verifier

SystemVerilog DPI Component Generation

HDL Verifier, used with Embedded Coder, lets you export a Simulink subsystem as a Verilog or SystemVerilog component with a Direct Programming Interface (DPI) for behavioral simulation. HDL Verifier creates a test bench to verify the generated component using data from the Simulink model. HDL Verifier also allows you to customize the generated SystemVerilog file, including the ability to tune parameters in the generated SystemVerilog module at simulation time.

The supported HDL Simulators include:

  • Mentor Graphics ModelSim and Questa
  • Cadence Incisive
  • Synopsys® VCS®
SystemVerilog DPI Component Generation
SystemVerilog DPI Component Generation.
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