HDL Verifier

Transaction-Level Model Support

When used with Simulink Coder, HDL Verifier automatically generates IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models. Generated SystemC models have a TLM 2.0 compliant interface with a target socket that uses the TLM 2.0 generic payload. You can select options for memory mapping, processing times, and input and output buffering. HDL Verifier also generates a SystemC test bench and a report that helps you navigate the generated code.

Next: SystemVerilog DPI Component Generation

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Auf den FPGA gebracht: Prototyping und Verifikation von Algorithmen auf digitaler Hardware

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