Live-Webinar

A Guided Workflow for Zynq Using MATLAB and Simulink


With the introduction of the Zynq-7000 All-Programmable System on Chip (AP SoC), which includes FPGA fabric and ARM microcontroller cores on a single chip, Xilinx has created a platform that can enable high-performance systems, but requires engineers to engage in both software and hardware development processes to yield the best Zynq system performance.

In this webinar, we will demonstrate a new guided workflow for Zynq using MATLAB and Simulink. We will explore Model-Based Design and show how this methodology can be used to speed up your system development process. We will then apply a Model-Based Design approach to application development on the Xilinx Zynq-7000 SoC, highlighting automatic HDL code generation for the FPGA fabric on Zynq and automatic C-Code generation for the ARM MCU, along with automatic generation of the required interface logic and software between the FPGA and ARM.

Please allow approximately 60 minutes to attend the presentation and Q&A session.

Who should attend: FPGA designers, embedded systems developers, and systems engineers who are evaluating the Xilinx Zynq SoC for an upcoming design.

Highlights:

  • Integrated Hardware / Software workflow for Zynq
  • Automatic HDL Code generation
  • Automatic C Code generation
  • Automatic interface logic and code generation

Die Arbeitsweise der folgenden Werkzeuge wird gezeigt

  • HDL Coder™
  • Embedded Coder®
  • Simulink®