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Modeling and Simulation of an All-Digital Phase-Locked Loop

Russell Mohn, Epoch Microelectronics

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Modeling and Simulation of an All-Digital Phase-Locked Loop

This presentation describes both a phase-domain model and time-domain model of an all-digital phase-locked loop (ADPLL). We emphasize using the models to derive specifications for PLL subblocks such as the phase-frequency detector and voltage-controlled oscillator. In addition, the models are to derive the specifications for an example fractional-N ADPLL covering 2 GHz to 3 GHz.